In conventional polysilicon-gate CMOS technologies, there is nearly always an nFET associated with one pFET in a given circuit, where the two FETs have a common input. In the corresponding structure a single polysilicon gate structure is shared by the corresponding nFET and pFET, allowing close placement of the nFET to the pFET and also enabling a single contact to provide a path from the wiring to both gates. This results in superior circuit density.
In some versions of CMOS that employ metal-gate/high-k gate-dielectric stacks, the pFET and nFET gate stacks differ from one another in order to accommodate optimal nFET and pFET properties, such as drive current, immunity from short-channel effects, and leakage. As a result nFET/pFET pairs of device that electrically share a gate cannot physically share a gate as in the case of polysilicon-gate CMOS technology. Hence the metal-gate/high-k gate-dielectric stack device pairs will occupy more physical space and result in lower circuit density, increased production cost, and increased circuit power.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.